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74LVTH16244
LOW VOLTAGE BICMOS 16 BIT BUS BUFFER WITH BUS HOLD AND POWER UP 3-STATE
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HIGH SPEED: tPD = 3.2ns (MAX.) at TA = 85C VCC = 3.0V LOW POWER DISSIPATION HIGH LEVEL OUTPUT: ICC = 190A (MAX.) at TA = 85C OUTPUT IMPEDANCE: |IOH| = 32mA, IOL = 64mA (MIN at VCC = 3.0V) |IOH| = 8mA, IOL = 24mA (MIN at VCC = 2.7V) BALANCED PROPAGATION DELAYS: tPLH tPHL POWER DOWN PROTECTION ON INPUTS AND OUTPUTS COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN),VIL = 0.8V(MAX) at VCC = 2.7 to 3.6V POWER-UP/DOWN 3-STATE: IOZPU = 100A MAX at VCC = 0V to 1.5V, VCC = 1.5V to 0V, TA = 85C BUS HOLD PROVIDED ON DATA INPUTS OPERATING VOLTAGE RANGE: VCC(OPR) = 2.7V to 3.6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES H16244 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)
TSSOP
TFBGA
ORDER CODES
PACKAGE TSSOP48 TFBGA54 T&R 74LVTH16244TTR 74LVTH16244LBR
LOGIC DIAGRAM
DESCRIPTION The 74LVTH16244 is a low voltage BiCMOS 16 BIT BUS BUFFER (NON-INVERTED) fabricated with sub-micron silicon gate and five-layer metal wiring BiCMOS technology. It is ideal and full specified for hot-insertion and high speed 3.3V applications; the power-up/down 3-state circuitry places the outputs in the high impedance state during power-up/down, which prevents driver conflict. This function is guaranteed when VCC is between 0 and 1.5V. It can be interfaced to 3.3V signal environment for both inputs and outputs. Any nG output control governs four BUS BUFFERS. Output Enable input (nG) tied together gives full 16-bit operation. When nG is LOW, the outputs are on. When nG is HIGH, the output are in high impedance state effectively isolated. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistors. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage.
February 2004 1/13
74LVTH16244
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TFBGA PIN No A3, J3 A6, B5, B6, C5, C6, D5, D6, E5, E6, F5, F6, G5, G6, H5, H6, J6 A1, B2, B1, C2, C1, D2, D1, E2, E1, F2, F1, G2, G1, H2, H1, J1 J4, A4 D3, D4, E3, E4, F3, F4 A2, A5, B3, B4, H3, H4, J2, J5 C4, G4, C3, G3 TSSOP PIN No 1, 24 47, 46, 44, 43, 41, 40, 38, 37, 36, 35, 33, 32, 30, 29, 27, 26 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 16, 17, 19, 20, 22, 23 25, 48 4, 10, 15, 21, 28, 34, 39, 45 42, 31, 7, 18 SYMBOL 1G, 4G 1A1-4,2A1-4 3A1-4, 4A1-4 1Y1-4,2Y1-4 3Y1-4, 4Y1-4 3G, 2G GND NC VCC NAME AND FUNCTION Output Enable Inputs Data Inputs Data Outputs Output Enable Inputs Ground (0V) No Connected Positive Supply Voltage
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74LVTH16244
PIN CONNECTION (top view for TSSOP, top through view for BGA)
TSSOP TFBGA
TRUTH TABLE
INPUTS nG L L H
Z = High Impedance; X = Don't care, n = 1..4, x = 1..4
OUTPUT xAn L H X xYn L H Z
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74LVTH16244
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO VO IIK IOK IO IO ICC Pd Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (Output disabled) DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current low state DC Output Current high state DC VCC or Ground Current Power Dissipation (*) Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to VCC + 0.5 - 50 - 50 128 64 100 400 -65 to +150 300 Unit V V V V mA mA mA mA mA mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW: 65C derated to 300mW by 10mW/C: 65C to 85C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO VO Top dt/dVCC dt/dv Supply Voltage Input Voltage (An, nG) Output Voltage Output Voltage (Output Disabled) Operating Temperature Minimum Power-up ramp rate Input Rise and Fall Time (note 1) Parameter Value 2.7 to 3.6 0 to 3.6 VCC 3.6 -40 to 85 200 0 to 20 Unit V V V V C s/V ns/V
1) VI from 0.8V to 2.0V at VCC =2.7V to 3.6V
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74LVTH16244
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 2.7 2.7 3.3 (*) 2.7 3.3 (*) 3.6 3.6 3.0 3.0 3.6 VOH High Level Output Voltage 2.7 2.7 3.0 VOL Low Level Output Voltage 2.7 2.7 3.0 3.0 3.0 IOZ High Impedance Output Leakage Current 3.6 VI = GND or VCC VI = GND or VCC nG = GND VI = 0.8V VI = 2.0V VI = 0 to 3.6V IO = -100 A IO = -8 mA IO = -32 mA IO = 100 A IO = 24 mA IO = 16 mA IO = 32 mA IO = 64 mA VO = 0.5V or 3.0V VI = VIL or VIH nG = VCC VO = 0.5V or 3.0V VI = GND or VCC nG = GND or VCC VO = 0.5V or 3.0V VI = GND or VCC nG = GND or VCC VI = GND to 3.6V VO = GND to 3.6V VO = High, IO = 0 VO = Low, IO = 0 nG = VCC, IO = 0 VO = GND or VCC ICC Maximum Quiescent Supply Current / Input (An or nG) 3.3 (*) VI = VCC - 0.6V An,nG = VCC or GND 2.5 2.4 2.0 0.2 0.5 0.4 0.5 0.55 5 A V V IIK = -18mA TA = 25 C Min. Typ. -0.85 2.0 2.0 0.8 0.8 0.8 0.8 1 1 135 -135 75 -75 500 A Max. Value -40 to 85 C Min. Max. -1.2 2.0 2.0 V V V A A A Unit
VIK VIH VIL II
Input Voltage Clamp (An, nG) High Level Input Voltage (An, nG) Low Level Input Voltage (An, nG) Control Input Leakage Current Data Input Leakage Current
II(HOLD) Data Input Hold Current
IOZPU
High Impedance Output 0 to 1.5 Leakage Current High Impedance Output 1.5 to 0 Leakage Current Power Off Leakage Current Quiescent Supply Current 0 3.6
100
A
IOZPD
100
A
IOFF ICCA
100 0.19 5.0 0.19 0.2
A mA
mA
(*) Power Supply Range VCC = 3.30.3V
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74LVTH16244
AC ELECTRICAL CHARACTERISTICS
Value Symbol Parameter Test Condition VCC = 2.7V Min. tPLH tPHL tPZL tPZH tPLZ tPHZ tOSLH tOSHL Propagation Delay Time An to Yn Propagation Delay Time An to Yn Output Enable Time nG to Yn Output Enable Time nG to Yn Output Disable Time nG to Yn Output Disable Time nG to Yn Output To Output Skew Time (note1, 2) TA = - 40 to 85 C Max. 3.7 3.7 5.0 5.0 4.4 5.0 VCC = 3.3 0.3V Min. 1.2 1.2 1.2 1.2 2.0 2.2 Typ. 2.5 2.5 2.7 2.7 3.7 4.4 Max. 3.2 3.2 4.0 4.0 4.2 5.1 0.5 ns ns ns ns ns ns ns Unit
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn| 2) Parameter guaranteed by design
CAPACITANCE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) open 3.3 Value TA = 25 C Min. Typ. 6 15 Max. -40 to 85 C Min. Max. pF pF Unit
CI CO
Control Input Capacitance Output Capacitance
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ (VCC = 3.0 to 3.6V) tPZL, tPLZ (VCC = 2.7V) tPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open 6V 6V GND
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74LVTH16244
WAVEFORM SYMBOL VALUE
Symbol 3.0 to 3.6V VIH VM VX VY 2.7V 1.5V VOL +0.3V VOH -0.3V VCC 2.7V VCC 1.5V VOL +0.15V VOH -0.15V
WAVEFORM 1: PROPAGATION DELAY (f=1MHz; 50% duty cycle)
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74LVTH16244
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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74LVTH16244
TSSOP48 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.50 6.0 0.5 BSC 8 0.75 0 0.020 0.17 0.09 12.4 8.1 BSC 6.2 0.236 0.0197 BSC 8 0.030 0.05 0.9 0.27 0.20 12.6 0.0067 0.0035 0.488 0.318 BSC 0.244 TYP MAX. 1.2 0.15 0.002 0.035 0.011 0.0079 0.496 MIN. TYP. MAX. 0.047 0.006 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
7065588C
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74LVTH16244
TFBGA54 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 B D D1 E E1 e SE 5.4 0.25 0.78 0.35 7.9 6.4 5.5 4 0.8 0.4 5.6 212.6 0.4 0.86 0.45 8.1 TYP MAX. 1.2 9.8 30.7 13.7 311.0 252.0 216.5 157.5 31.5 15.7 220.5 15.7 33.8 17.7 318.9 MIN. TYP. MAX. 47.2 mils
7390143/C
10/13
74LVTH16244
Tape & Reel TSSOP48 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.7 13.1 1.5 3.9 11.9 12.8 20.2 60 30.4 8.9 13.3 1.7 4.1 12.1 0.343 0.516 0.059 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.350 0.524 0.067 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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74LVTH16244
Tape & Reel TFBGA54 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 3.9 7.9 6.1 8.6 1.8 4.1 8.1 0.153 0.311 12.8 20.2 60 22.4 0.240 0.339 0.071 0.161 0.319 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 MIN. TYP. MAX. 12.992 0.519 inch
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74LVTH16244
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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